_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<sensille> is there any documentation how to run a simulation on a project? i have no idea where to start. https://github.com/sensille/litehm2/blob/master/litehm2.py
<sensille> I managed to manually simulate the design in modelsim, but what do i have to do to run the builtin verilator wrapper?
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