_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<sensille> can i tell litescope to record the startup?
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<_florent_> jevinskie[m]: I was also doing this mistake and it was pretty painful to have to recompile just for this... and it was only visible in the verilog since CSRs were correctly collected.
<_florent_> sensille: If recording signal just after startup: this is not really supported. But you could add a reset to the core you want to observe at startup, control this reset over a CSR and trigger LiteScope on this reset
<sensille> there is a reset csr but it does nothing to how the cpu behaves. i'm still totally at loss what's going on here, need to poke at it a few more days
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