<sensille>
okay, one problem seems to be that etherbone cannot handle the initial back-to-back packets from litescope_cli, maybe when sys_freq is too low (50MHz)
<sensille>
etherbone locks up after that
<sensille>
adding a sleep in litex_server makes litescope work again
<sensille>
adding a ping-pong for writes would help
<sensille>
or a 10ms sleep after each write
<sensille>
oh, or is it because the cpu is hogging the bus?
<sensille>
finally a bit of progress: with neorv32 i can get a small program to run, just not with vexriscv. the vexriscv core just runs up the instruction counter, fetches the instruction, but doesn't seem t execute anything. loops from 0-0x1e8
<riktw>
I got a small issue with interrupts. I want to add a second uart and a second timer to a SoC and have interrupts. I added the following ( https://pastebin.com/r8FENm3X ) to an example from the litex-boards and it builds and they got added to the SoCIRQHandler.
<riktw>
In the software/libbase/isr.c I added a small printf to print any irq source other then the build in uart but I can't seem to generate an interrupt. Is there anything else needed, or am I missing something in code? ( https://pastebin.com/9Apyx37a )
<riktw>
I also saw that I can do self.irq.add("fjnefji", use_loc_if_exists=True) with anything for the name and it does compile? Is that the expected behavior?