02:20 <jevinskie[m]> But the Amaranth compat is getting bulldozed =\ https://github.com/amaranth-lang/amaranth/issues/692

02:21 <jevinskie[m]> Oh, I see LiteX's move is going to change that

02:21 <jevinskie[m]> :)

02:28 <cr1901> jevinskie[m]: Yes, compat layer remains for now, and I've repeatedly bugged _florent_ about using it lol

05:32 <sensille> oh, amaranth :)

07:04 <_florent_> cr1901: It will be interesting to have this in place, to allow users willing to only use Amaranth and also to do more testing. I'll probably still have to Migen for several projects I maintain (at least until things are closely analyzed), but if we can switch between Migen/Amaranth easily, this will already be a good step.

07:38 <sensille> okay, down to 45 timing errors in eth_tx_clk on ecp5. storage_2_storage_2_0_0 -> tx_gap_source_payload_data. maybe i can add register somewhere in that path

08:05 <sensille> tx_cdc

08:47 <sensille> setting the cdc to buffered achieves timing closure, not it only has to work

13:13 <cr1901> _florent_: It also means the compat layer gets used for its intended purpose (it was made for LiteX IIRC) :D

13:14 <cr1901> _florent_: Also, are you aware of any restrictions adding an SPIFlash to LiteX designs and then booting from it? I can simplify in a bit, but I have a LiteX invocation that fails to jump to RAM if --with-spi-flash is specified, but works without that argument (serial and flash boot)

20:13 <_florent_> cr1901: I don't see an obvious reason, if you can share the code, I could look.

20:31 <cr1901> _florent_: I will minimize and get back to you