<_florent_>
sensille: For simulation with verilator, you can create a simulation target, that will be very similar to your FPGA target, but that will use PHY models and Verilator stubs.
<sensille>
_florent_: i tried to use litex_sim as an inspiration, but everything is different there. i currently don't need to simulate the phys. i really just want to run the design as-is, especially because small changes in the design can break it (or make it work)
<sensille>
so i really only want to send the result to verilator
<sensille>
doesn't seem to be so easy anyway: %Error-UNSUPPORTED: /usr/local/diamond/3.12/cae_library/simulation/verilog/ecp5u/EHXPLLL.v:1121:8: Unsupported: Verilog 1995 deassign
<tnt>
Yeah, I wouldn't expect sim models from lattice to go through verilator.
<tnt>
You either need a real verilog simulator or code up your own sim models / stubs.