_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<sensille> jevinskie[m]: oh, nice, that helps, thanks
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<keesj1> LiteX was mentioned quite a few times at the free silicon conference this week.
<tnt> Ooooohhhhh ... I'm trying to upgrade project to 2023.4 and I already fear the changes in the pcie dma.
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<tnt> Ok, so interestingly it seems the DMA frontend upstream has now been modified to do ... exactly what I used to patch it to do.
<tnt> (well, equivalent to at least). By 3f040ac9c61db5dd357eab7289d471de0422b0b7 . So that now in prog_mode, the index is no longer just "reset" to 0 when the table happens to be empty.
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<_florent_> tnt: This was a request from a client. Otherwise, since this DMA is use on different projects with their own software, the changes should only be fixes or additional features, so I don't expect that much issue with your update (at least on this point)
<tnt> _florent_: Well the default litepci driver uses loop mode, but I've always used 'prog_mode' with my own driver.
<tnt> But before this change, prog mode wasn't really all that useful TBH, which is why I was already patching the hw. Now I can just use upstream.
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<_florent_> prog_mode was indeed just used during the programmation before.
<tnt> _florent_: Did anything change in the way CSR are created when using LiteXModule vs just Module,AutoCSR ? Or just with some recent changes ?
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