_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<jersey99> Hi all, quick q: Is there a way to get hold of the CSR information just before litex calls platform.build(), from a user method?
<jersey99> I have some CSRs, that I want to export to a csv with some custom information, and I don't want to wait until platform.build is complete :-/
<josuah> jersey99: is csr.csv not what you need? I think it is already generated by LiteX?
<josuah> Oh you mean not needing to wait the RTL elaboration time
<jersey99> yes, also, I need some more info about csrs than what is inside csr.csv. For eg, bitwidth of the csr storage, it's reset value, etc
<josuah> Is the goal to generate datasheets? Just curious.
<jersey99> yes, something like this, but not a datasheet at all. I just want to export some CSRs internal to the non-soc design
<jersey99> non-cpu side of the design
<josuah> oh right!
<josuah> it seems to live around litex/litex/soc/integration/export.py:
<josuah> which roots aaall the way back to Migen
<jersey99> yes, for now I managed to get what I want by fudging export.py, but it would be nice to have a hook/function like do_finalize that gets called just before VNS stuff gets generated, but after the finalize is called (?)
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