_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<Shatur> Hi! I generated svd and memory from litex_sim, but have the following linker error: section '.text.dummy' will not fit in region 'spiflash': overflowed by 18446744073675997184 bytes
<Shatur> Is that too many bytes? Does this mean that the generated memory and svd are invalid?
<geertu> Shatur: 18446744073675997184 = 0xFFFFFFFFFE000000 = -0x2000000
<Shatur> Yes, looks like an overflow?
<geertu> Shatur: Any chance the llinker script has some symbols in the wrong order?
<Shatur> geertu: here is how my memory.x look: https://pastebin.com/N6mCQskr
<tpb> Title: memory.x - Pastebin.com (at pastebin.com)
<Shatur> I use rust
<geertu> Shatur: There's no spiflash under MEMORY? Perhaps you meant rom?
<Shatur> geertu: oh, sorry, it's a wrong file with my experiments :) Here is the right one: https://pastebin.com/MBFcfBNZ
<tpb> Title: memory.x - Pastebin.com (at pastebin.com)
<geertu> Shatur: Change _stext to 0x01000000?
<geertu> Currently, it's at -32 MiB from the end of spiflash
<geertu> Hmm, as it is CPU reset, it should stay at zero.
<geertu> But you should make sure it ends up in rom, not in spiflash.
<Shatur> geertu: it worked, thank you!
<Shatur> But why litex_sim generates it this way? Is it a bug?
<Shatur> Here is what I used to generate it: litex_sim --csr-svd=hal/litex_sim_pac/soc.svd --memory-x=hal/litex_sim_pac/memory.x --with-spi-flash
<geertu> Shatur: sorry, no idea
<geertu> _florent_: ^
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<Shatur> Is it possible to connect to litex_sim via serial? I trying to print something via UART.
<Shatur> In simulator it shows --============= Liftoff! ===============-- and nothing after it. Is it something wrong with the firmware or I just need to connect to the simulator somehow?
<Shatur> Oh, I see, it prints UART to console by default using uart2console module. Probably something wrong with printing code.
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