_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<cr1901> _florent_: I want to a bit more cleanup of my litex folder... can you confirm that both liteusb and litehyperbus are gone from litex and I can safely rm -rf the repos?
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<_florent_> cr1901: you can remove them yes. liteusb code has been moved to LiteX. Same for litehyperbus's generic core; the ECP5 DDR version is still in litehyperbus repo (but we no longer install it by default)
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<jevinskie[m]> Ugh, I hope I can leave most of these signals unused. This is a gige transceiver for an arria 10 https://gcdnb.pbrd.co/images/MT3dO1PxMSgT.png?o=1
<_florent_> jevinskie[m]: You can do things similarly to the other wrapper: Have an FSM managing the TX/RX init and then just TX/RX streams for the data.
<_florent_> jevinskie[m]: You can probably start from an example from Intel/Altera and create the wrapper progressively from it.
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