07:49 <leons> jevinskie: Re Gidel HawkEye Arria 10 FPGA, I've never used Altera/Intel FPGAs before and heard quite the horror stories about the toolchain, coming from people who are used to FPGA tooling, so that scares me quite a bit ^^

07:50 <leons> How workable is the Intel tooling compared to Xilinx, when used with a DSL such as Migen or full-blown SoC framework such as LiteX?

07:52 <leons> Although I'm currently trying to work on a cocotb extension for the Xilinx MIG native interface and that's nuts as well, so perhaps it's all a question of perspective.

08:02 <jevinskie[m]> You can use the altera qsys gui or tcl scripts to instantiate the IP in do_finalize() and then add it to litex using an Instance(). I’ve done it for simple stuff like an avalon memory mapped GPIO peripheral but not for more complex stuff like transceivers or dram blocks.

15:24 <rah> can I ask why litex was created when fusesoc already existed?

17:09 <_florent_> rah: the project have different purposes, both FuseSoC/LiteX can be used to integrate cores, but FuseSoC is more focused on reuse of existing cores while LiteX provide cores/interconnect/integration/debug tools (basically all you'll put around a CPU) to create your own SoC.

21:16 <somlo> rah: fwiw, a few years ago I was trying to slap together a linux-capable 64-bit system built around rocket chip, from various free/open IP blocks I was scavenging from around the Internet (started with LowRisc, tried replacing the proprietary bits)

21:16 <somlo> I came to LiteX for the dram controller, stayed when I noticed it has everything else I need as well :D