05:35 <shorne> shenki: FYI, I am working on adding MTTCG to openrisc, the issue you noticed about smp failing after 4 threads is kind of interesting

05:36 <shorne> I am tracking it down, I traced it so far to the kernel getting blocked during bootup trying to run a migration i.e. 'multi_cpu_stop' to set the clocksource

05:36 <shorne> one of the CPU's cannot stop because it gets stuck trying to handle an interrupt that QEMU just keeps asserted

05:37 <shorne> I haven't tracked it down yet, but almost there

07:38 <shorne> I think I see the issue, we have the same IRQ lines attached to all CPU's, when an irq is lowered its only triggering that on the local CPU

11:17 <shorne> ok, maybe I got it working, I don't think the level triggered interrupt driver is correct in the kernel

11:18 <shorne> 4 cores now boots stable

12:04 <acathla_> _florent_, the last commit of soc/export.py generates lines like that : #define CSR_CTRL_BASE CSR_BASE + 0x0L, while it was generated like this : #define CSR_CTRL_BASE (CSR_BASE + 0x0L)

12:05 <acathla_> It seems to be the same, unless you make some calculations in the prepocessor that does not work anymore, like : _Static_assert( CSR_IR_RX2_BASE - CSR_IR_RX1_BASE == IR_RX_BASE_DELTA, "IR2 base address not aligned" );

12:06 <acathla_> I mean, #define IR_RX_BASE_DELTA (CSR_IR_RX1_BASE - CSR_IR_RX0_BASE) gives an empty IR_RX_BASE_DELTA

12:17 <acathla> Hum, it works if add the parenthesis later: #define IR_RX_BASE_DELTA (CSR_IR_RX1_BASE) - (CSR_IR_RX0_BASE)

12:17 <acathla> Seems to be expanded at the very end

17:55 <_florent_> acathla: https://github.com/enjoy-digital/litex/commit/d1a456a545bd65ce2effd2c3882d5a3dd0452cdd :)

20:48 <acathla_> _florent_, thanx, that's much better than my ugly patch