07:02 <Seth25> Hi, I am trying to port LiteX to the Upduino 2.0 and have the platform/target files about 99% there I think, but I can't figure out the clock. I believe the Upduino 2.0 only has the internal clock unless you connect the clock output to a pin with a jumper of some sort. I can't figure out how to tell LiteX to use the internal oscillator for a clock

07:02 <Seth25> signal. Anyone know how to do that? The Upduino 2.0 uses an ICE40UP5k FPGA (same as Icebreaker)

10:55 <_florent_> Seth25: This is for ECP5, but this should be very similar on iCE40: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/colorlight_i5.py#L51-L54

10:57 <_florent_> mithro: I just did a quick update of the doc: Added missing cases: Artix7/DDR2 (NexysA7), Ultrascale/DDR3 (Decklink Quad HDMI Recorder) and also added ECP5 for SDR/DDR3 + RPC DRAM for DDR3/Artix7

12:54 <sammhho> hi all

12:55 <sammhho> anyone having success running gdbserver or gdb within buildroot Linux on a Vexriscv SoC ?

12:56 <sammhho> when i run a full gdb within the buildroot it gives `-sh: gdb: Text file busy` from the busybox shell

15:13 <bentomo> Is there a way to do a "make clean" like command for the gen.py?

15:37 <_florent_> bentomo: not really, rm -rf build should work :)

15:51 <mithro> _florent_: Thank you!

15:56 <_florent_> mithro: BTW, we could also add Artix Ultrascale + :): https://twitter.com/FPGA_Zealot/status/1534058473545027584

15:56 <mithro> That would be awesome!

15:56 <_florent_> and https://twitter.com/FPGA_Zealot/status/1534184505266778114

15:58 <mithro> _florent_: Did you see that my team launched https://developers.google.com/silicon ? (Associated blog post - https://bit.ly/gdevsilicon).

15:58 <tpb> Title: Silicon  |  Google Developers (at developers.google.com)

16:06 <bentomo> _florent_: got it, Thanks! By the way, so far in my litedram adventures I found that while trying to generate a litedram core with serv in it, the bios did not fit in the default rom size. Not sure if it's worth opening an issue yet as I'm still learning and could be doing something wrong.

16:10 <_florent_> mithro: Thanks, I indeed saw this. It seems your efforts are gaining traction internally, congrats :)

16:11 <_florent_> mithro: I edided the document and splitted Ultrascale in Artix/Kintex/Virtex

16:12 <_florent_> mithro: we should also probably compare things to MIG instead of MCB from Spartan6

16:15 <_florent_> bentomo: in LiteX targets, the ROM is automatically resized to the size of the binary at the end of the SoC generation, but not sure this has been applied to the generator. I could have a look if you think there is an issue.

16:20 <bentomo> _florent_: My workaround was to manually increase the rom size on line 859 of gen.py in the current commit to up the rom size. I could blanket post my yaml here if you'd like if you want to reproduce it. Just asking before I attach files if this is the appropriate place for it

16:47 <mithro> _florent_: the MCB is just an artifact of how old that spreadsheet is :-)

17:07 <mithro> _florent_: Is the support for Ultrascale or Ultrascale+ ?

20:00 <_florent_> mithro: the PHY is the same on Ultrascale/Ultrascale+ :) : https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/usddrphy.py#L494-L498

20:04 <mithro> _florent_: oh! That is super interesting

20:04 <mithro> _florent_: is there a difference between artix / kintex / virtex?

20:23 <jevinskie[m]> I’m looking at the transceiver IP from intel for arria 10 and my eyes are bleeding. It’s so friggin complicated 🫠

23:39 <bentomo> One other general thing I'm having trouble figuring out. How does the bios.elf make it into the rom? The output says it was loaded but I don't see any tcl commands that load bram or it being hard coded in the memory verilog file. Currently generating a bit stream sand going to yolo it but not sure if I'll get any output