01:53 <jevinskie[m]> Sounds like a linker script issue

04:55 <jevinskie[m]> I'm working on hooking up the slowDDR3 system interface to LiteX by presenting it as a wishbone bus. The system interface only supports 16-bit reads/writes - is there a ready made solution I can use to enable byte-wide access suitable for a CPU's main memory/wishbone attachment or do I need to write up a read-modify-write FSM myself?

04:59 <MoeIcenowy> jevinskie[m]: if it's DRAM, it should have DM from the beginning I think

05:01 <jevinskie[m]> Right, but its not exposed by slowDDR3's system interface. I'm not familiar enough with it to add a dm/sel signal to its sys interface. https://github.com/ZiyangYE/General-Slow-DDR3-Interface/blob/main/slowDDR3.scala#L66-L70

05:02 <jevinskie[m]> maybe its just as simple as combinatorially fishing it through?

05:04 <MoeIcenowy> I asked the author

05:10 <jevinskie[m]> Thanks a bunch!

05:11 <jevinskie[m]> Hah yeah looks like I just need to fish it through, I shouldn’t be so afraid :) `phyIO.dm := 0` (const driver of dm in slowDDR3)

05:12 <jevinskie[m]> SpinalHDL is quite impressive, I wish I knew Scala/functional style better.

06:15 <jevinskie[m]> I think this will work once I get the litex side working. I have some old litex code about mapping sram to WB laying around I need to copypasta :) https://github.com/jevinskie/General-Slow-DDR3-Interface/commit/df6d62598c225f2a5ef7db3718f77c445a62b795

06:18 <jevinskie[m]> Hmm that can’t be right, I have dm inverted (11) in the write case. Test bench passed though? 😬

08:49 <jevinskie[m]> Ah the test only goes up to 32 kwords, the test data is just the counter. Bump it up to 65 kwords and it shows the issue about driving dm wrong. Glad the simulation model works!

08:55 <Shatur> Unable to build my pac crate because of the following error: rust-lld: error: section '.text.dummy' will not fit in region 'spiflash': overflowed by 18446744073675997184 bytes

08:55 <Shatur> The size looks to big. Is something wrong with svd generation? I generated it from litex_sim.

09:44 <jevinskie[m]> <Shatur> "Unable to build my pac crate..." <- Sounds like a linker script issue to me. is text quite far away from that spiflash section?

09:47 <Shatur> <jevinskie[m]> Here is how my memory.x looks: https://pastebin.com/88q0Qhz5

09:47 <tpb> Title: MEMORY { rom : ORIGIN = 0x00000000, LENGTH = 0x00020000 sram : ORIGIN = 0x10 - Pastebin.com (at pastebin.com)

09:48 <Shatur> I just learning stuff, trying to build a hello world, but don't have a real hardware. So I used lite_sim to generate memory and svd for me.

09:50 <Shatur> I used this repo as an example: https://github.com/icebreaker-fpga/icebreaker-litex-examples. I can sucesfully build it with svd and memory from icebreaker. But I replace it with generated data from litex_sim - I have the mentioned error.

09:50 <Shatur> So I suspecting that the problem in the generated memory.x or/and svd file.

18:54 <lambda> _florent_: hey, could you chime in on https://github.com/enjoy-digital/liteeth/issues/114? standalone wishbone liteeth cores seem to be completely broken right now because they don't actually expose a wishbone interface.

19:01 <lambda> I'm guessing it's because of https://github.com/enjoy-digital/liteeth/commit/8733aecf89d56e1215dedd491bcd8fdea3fb21d9; not sure if removing the IOs counts as a "minor cleanup/simplification" :)

20:53 <_florent_> lambda: I'll look at it on Monday

21:04 <lambda> _florent_: thanks!