00:44 <mithro> FYI - https://antmicro.com/blog/2022/05/faster-soc-interconnects-with-test-driven-fpga-development-and-cocotb/

00:44 <tpb> Title: Antmicro · Speeding up SoC interconnects with test-driven FPGA development using Cocotb (at antmicro.com)

10:55 <_florent_> mithro: thanks, now I better understand the PR (sadly for Antmicro I also asked to have regression test for this in LiteX, so they probably had to duplicate part of the cocotb tests in the unit-test :))

14:34 <Guest58> hello please, I have a question concerning litedram

14:34 <tnt> ask, don't ask to ask.

14:38 <Guest58> I am new to Litex world I have a problem when trying to run gen.py it says that it needs config argument and when I add it says the file is not found so do; I need to download it or create one or what I should do?

15:23 <_florent_> Guest58: (if reading the logs): you need to provide a configuration file to litedram_gen, you can find some examples there: https://github.com/enjoy-digital/litedram/tree/master/examples

15:23 <_florent_> ex: litedram_gen arty.yml

15:25 <_florent_> you can find some examples of integration here: https://github.com/antonblanchard/microwatt/tree/master/litedram

15:26 <_florent_> or here: https://github.com/chipsalliance/Cores-SweRVolf/tree/master/cores/litedram

17:57 <Guest34> Hello, I am a new user of LiteX. My target board is digilent_arty.py and am trying to build a SoC with VexRISCV plus some peripherals. If I disable gateware compilation and software compilation, my flow runs. If I enable these compilations, I get an issue - the Makefile cannot find the location of SOC_DIRECTORY variable. Has anyone else seen this

17:57 <Guest34> issue ?

18:39 <sajattack[m]> it looks like soc_directory is supposed to point to the build directory of your board

18:39 <sajattack[m]> so like litex/litex-boards/litex_boards/targets/build/digilent_arty/ for example

18:40 <sajattack[m]> it looks like it's defined here https://github.com/enjoy-digital/litex/blob/b020d4cf62f20bffa4ce3c262c9c9c85802abe68/litex/soc/integration/builder.py#L61

18:42 <sajattack[m]> also I came to say liteluna looks cool and congrats on the progress with litesata

19:00 <Guest34> sajattack[m] : Thank for the response. In my sub-directory ./litex-boards/litex_boards/targets/ I do not see a build sub-directory at all. However I see ./litex-boards/litex_boards/targets/digilent_arty.py . Any thoughts ?

19:01 <sajattack[m]> well it would be where-ever you run the script from

20:20 <somlo> _florent_: after 89fdb498 (I think, it's the first one to break my build, but the error is different than what I get with master) I can no longer build rocket/litex (on nexys_video, in particular)

20:21 <somlo> the error is "pythondata_software_picolibc/data/meson.build:35:0: ERROR Compiler riscv64-unknown-elf-gcc can not compile programs"

20:31 <_florent_> somlo: thanks for the feedback, can you add a print of the binutils version here?: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/export.py#L101

20:32 <_florent_> and of the flags: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/export.py#L107

20:33 <_florent_> just in case, can you also try to do a clean build (rm -rf build)

20:34 <somlo> _florent_: first off, manually commenting out / reverting 89fdb498 gets things to work again for me, so it's definitely the culprit

20:34 <somlo> I always rm -rf the build directory before starting a build

20:36 <_florent_> somlo: ok, I did some fix on top of this commit to get it working on my setup, we would now need to understand what is different on yours

20:36 <somlo> so you want me to print out what it thinks the binutils version and flags are at the locations you pointed out?

20:37 <somlo> stand by, adding prints to my copy of the code...

20:37 <_florent_> yes, just to see if this triggers to workaround to add _zicsr to march

20:39 <_florent_> it could also be interesting to comment this:

20:40 <_florent_> https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/common.mak#L59-L61

20:40 <somlo> version is "2.37"; flags are "-mno-save-restore -march=rv64imafdc_zicsr -mabi=lp64 -D__rocket__ -mcmodel=medany"

20:41 <somlo> still the same issue with those lines commented out in common.mak

20:42 <somlo> btw, my command line is:

20:42 <somlo> rm -rf build/digilent_nexys_video; litex-boards/litex_boards/targets/digilent_nexys_video.py --build --cpu-type rocket --cpu-variant full4d --sys-clk-freq 50e6 --with-ethernet --with-sdcard --with-sata --sata-gen 1 --with-sata-pll-refclk

20:46 <_florent_> ok thanks, can you comment this: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/export.py#L109-L110

20:47 <somlo> yeah, seems to work fine with that portion commented out

20:50 <_florent_> ok, so while fixing the code I just made sure the behavior was as described in https://github.com/enjoy-digital/litex/pull/1279

20:50 <_florent_> on my setup, binutils is < 2.37, so I haven't been able to test this feature.

20:51 <_florent_> I'll have a closer look tomorrow

20:52 <somlo> for the record, my toolchain is github.com/riscv/riscv-gnu-toolchain commit 051b9f7 from Mar. 09, 2022 -- available pre-compiled from http://www.contrib.andrew.cmu.edu/~somlo/BTCP/RISCV-toolchain.tar.xz, in case that helps in any way