_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<DerekKozel[m]> Does anyone have an example of a LiteX system with a fairly simple Verilog or VHDL core wrapped and processing data streaming in/out on a Wishbone or AXI bus?
<tnt> This has a wrapped core connected to wishbone, also has a wrapped core connected to "AXI-Stream" (stream.Endpoint).
<tnt> (and in the root dir thereis examples/ with files actually using them)
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<cr1901> _florent_: Assuming alanvgreen agrees to this, is it possible to get this poster into the LiteX documentation? https://twitter.com/jevinskie/status/1528088344344662016/photo/1 I needed to reference it, and it's Just Plain Good.
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