_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<jevinskie[m]> Cool, I got Display() to work in FSMs
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<jevinskie[m]> DisplayEnter() only displays once when the state is entered, next up is emulating $monitor. Should be cake thanks to python :P
<_florent_> jevinskie[m]: nice!
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<rah> _florent_: my understanding of FuseSoC is that its focus on resuse of existing cores is in order to facilitate the creation of your own SoC, which is to say that the purposes of FuseSoC and LiteX seem to be the same, not different
<rah> the clue's in the name
<rah> "Its main purpose is to increase reuse of IP (Intellectual Property) cores and be an aid for creating, building and simulating SoC solutions." -- https://fusesoc.readthedocs.io/en/stable/user/introduction.html
<tpb> Title: Why FuseSoC? — FuseSoC 1.12.0 documentation (at fusesoc.readthedocs.io)
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<_franck_> rah: FuseSoC doesn't handle the interconnection by itself. You can configure which cores you need in your design and which tool you want to use for synthesis/simulation, FuseSoC will fetch all the cores and dependancies and build your design.
<_franck_> I see it like a super build tool
<_franck_> (well, I didn't use it for years so I may be wrong...)
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<jevinskie[m]> Here is that emulation of $monitor: https://gist.github.com/jevinskie/fc4fc7b36d9eade490816576b235fe6e