_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<jevinskie[m]> I’m having a bit of a brain fart. I’m trying to hook up the ddr3 model with the Tristates that the slowddr3 litex module wrapper uses from the platform.request pads. Can I use a record to hold the actual multi-valued logic and just pass them directly to the ddr3 model instance?
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<jevinskie[m]> Oh I think I can just pass a non-top level signal as target and just use that?
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