_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<sajattack[m]> triple-quotes are multiline strings I think
<sajattack[m]> r" is raw
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<_florent_> somlo: I'm not sure to remember if you got Debian booting with Rocket/LiteX but someone did it with your recently added quad core variant: https://twitter.com/AndrewC52207568/status/1460524569710661633
<acathla> Nice!
<somlo> _florent_: never really tried debian, but maybe I should -- was there a link with instructions, or just the tweet?
<somlo> if we get it working on the ecpix5, and get yosys/trellis/nextpnr packaged for Debian, it's "Mission Accomplished" on the self hosting stack goal :)
<geertu> somlo: I'm using a debootstrapped nfsroot for Starlight and PolarFire, so Debian definitely works on RV64
<geertu> somlo: yosys and arachne-pnr are available (nextpnt and trellis aren't)
<geertu> Unfortunately I'm stuck with buildroot on OrangeCrab, as VexRiscV is RV32
<somlo> I think Fedora is really close to working, I just never got over the mental barrier of diving into debugging systemd :P
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<DerekKozel[m]> Super minor point _florent_: The LitePCIe architecture image shows DMAN having AXI-ST RX0 rather than RXN. Same for the TX.
<somlo> also, I never tried Fedora (and systemd) on the genesys2 board (kintex, quad-full-rv64gc) -- maybe it's just the awful slowness of running with an emulated fpu on ecpix5 that causes it to time out. I should try that again (particularly now that opensbi works on full, gateware-fpu enabled rocket variants)
<_florent_> DerekKozel[m]: it seems to be gone :) Thanks
<_florent_> somlo: possible because I'm pretty sure the debian boot is Linux-on-LiteX-Rocket just ported to this Ali-Express Kintex7 board
<somlo> and, to be pedantic, opensbi works just fine on fpu-less rocket variants, it's just not emulating the fpu on behalf of the payload, and the paloads I happen to care about all expect to have an FPU :)
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<acathla> _florent_, the last fix is nice but now, instead of sending 64 bytes litex_term sends 60 only... https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_term.py#L466
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<acathla> Again, it's not critical for uploads to ram but it's non-aligned so not flash-friendly
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