_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<sajattack[m]> somlo: can you be my dts inspector? https://bpa.st/RCHA
<tpb> Title: View paste RCHA (at bpa.st)
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<geertu> sajattack[m]: Integrate in arch/riscv/boot/dts/ and run "make dtbs_check"?
<geertu> in Linux
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<sajattack[m]> thanks for the tip geertu
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<sajattack[m]> it seems more stable now 🎉 https://github.com/litex-hub/linux-on-litex-rocket/issues/19
<sajattack[m]> now I just need ethernet and sdcard :P
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<sajattack[m]> seems like I have metastability, not in my gateware, but in my linux images :P I tried to add lzrsz so I could transfer files over uart into ram, and that was enough to get back to a crashing linux
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<AndrewD> _florent_: Good news regarding you getting a Ti60 dev board. My Ti60 dev board will be here in about 2 weeks. Do you have an ETA?
<AndrewD> Resending some messages that didn't appear in the logs for some reason? I should give up on web irc clients....
<AndrewD> Another thing I have done some work on is integrating the CTU CAN FD IP core into litex. See: https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core
<tpb> Title: canbus / CTU CAN FD IP Core · GitLab (at gitlab.fel.cvut.cz)
<AndrewD> Would a litexcan project based on this core be useful / acceptable for Litex? The licencee is _almost_ MIT, but requires an agreement with the copyright holder for commercial use.
<AndrewD> Unfortunately I'm having issues getting the core operational in litex, not sure if it is because of GHDL->Yosys or something I've done wrong. If I share a tree would anyone be in a position to provide feedback?