01:58 <Aleksa> Hi all! I'm trying to fit my FPGA design into a smaller part by swapping out a MIG generated DDR3 controller with the litedram core. I've generated it standalone (to stay inside vivado for now) using gen.py. I noticed it came with a wishbone bus, I left it disconnected when I swapped the core in for the MIG controller and it doesn't seem to work at

01:58 <Aleksa> all. Is there any way this core can work off the bat like the MIG, or will I have to talk to it before it starts working?

06:23 <_florent_> Aleksa: You can generate a core very similar to MIG (with CPU/firmware) integrated for the calibration. That's what will do litedram_gen arty.yml for example

06:23 <_florent_> https://github.com/enjoy-digital/litedram/blob/master/examples/arty.yml

06:23 <_florent_> You can then customize the type of CPU (I generally use VexRiscv Min variant for this)

06:24 <_florent_> and the user ports

06:24 <_florent_> the calibration will be done automatically and reported on init_done /init_error outputs

06:40 <ejcspii> _florent_ Hi Florent, this is the addition to digilent_arty.py: https://pastebin.com/Ke8X25mU

06:40 <tpb> Title: WB test - Pastebin.com (at pastebin.com)

07:49 <_florent_> ejcspii: Thanks, it is also possible to share wb_test_slave.v? I could then test it myself

07:54 <ejcspii> _florent_ Here it is: https://pastebin.com/zZZc6cDD

07:54 <tpb> Title: module wb_test_slave( input wire i_clk, i_re - Pastebin.com (at pastebin.com)

07:55 <ejcspii> Never tried to do wishbone before. Thanks in advance!

08:07 <_florent_> ejcspii: I was able to reproduce the issue with litex_sim

08:07 <_florent_> ejcspii: and did a quick fix on the wb_ack in wb_test_slave.v

08:07 <_florent_> https://www.irccloud.com/pastebin/zmkn1VFM/

08:07 <tpb> Title: Snippet | IRCCloud (at www.irccloud.com)

08:07 <_florent_> https://usercontent.irccloud-cdn.com/file/ZnYHkyGt/Screenshot%20from%202021-11-26%2009-03-42.png

08:07 <AndrewD> _florent_: did you get the email about meeting to discuss collaboration?

08:09 <_florent_> AndrewD: Ah sorry, got it but forgot to answer after reading it.

08:11 <ejcspii> _florent_ Thank you, so I should not just ignore wb_cyc.

08:13 <ejcspii> And thanks for the diff, I'll look into the simulation myself.

14:28 <Aleksa> Florent: Thanks for the clarification! I set CPU to none, thinking it had to do with the rest of litex, but I now see that it's a very small CPU dedicated to calibrating the DDR3 controller. Can't wait to get it working tonight, between the low logic usage and the much faster compile time, the litedram core makes me never want to use MIG again lol

15:02 <tnt> So I used to include base/uart.h to get UART_EV_RX ... now that header seem gone and I don't see where to get that #define from.

15:04 <tnt> nm ...

15:15 <tnt> Next step is figure out how to unbreak the firmware build ... :/ I don't want any of the picolibc, I have all my own stuff.

15:17 <tnt> How do I disable the quiet build ? ( like instead of "CC firmware.elf" I want the full thing it's trying to do)

15:29 <cr1901> tnt: It's in the top-level Makefile how to disable the quiet build. If I remembered the exact invocation, I would tell you :P

15:30 <cr1901> https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/common.mak#L28-L40

15:30 <cr1901> Set V=1, presumably in the environment so GNU Make knows to steal that value for its own variables

15:32 <tnt> cr1901: yup tx, works.

15:33 <tnt> Looks like a bunch of my issues aren't actually litex but tinyusb having changed some stuff.

15:33 <cr1901> tinyusb himself appears to have vanished

15:33 <cr1901> His Twitter acct is gone, and my last email to him went unanswered

15:34 <tnt> Well there was a commit 4 days ago.

15:34 <cr1901> Oh? Hmmm...

15:35 <cr1901> Ohhh whoops

15:35 <cr1901> TinyFPGA*

15:35 <cr1901> It's too early in the morning

15:35 <cr1901> Ignore my comment- tinyusb* is pretty good at getting back to ppl.

15:35 <tnt> Oh yeah Luke Valenty is gone from OSS/Public stuff

15:36 <cr1901> Which is his prerogative, but I wish he at least notified ppl/xferred ownership of some repos.

15:49 <tnt> :/ Seem the picolibc stuff is hardcoded I don't easily disable it.

15:50 <cr1901> No, and the picolibc stuff was one reason I wanted to port all of litex to meson- so everything could be under a single ninja file

15:51 <tnt> I have my own printf and stuff like that, I don't want any of theirs :/

15:51 <cr1901> (ninja is not GNU makeserver-compat either, so a top-level make will spawn "ncores" make instances and "ncores + 2" ninja instances

15:52 <cr1901> I'm pretty sure there was a commit recently to skip building picolibc tho