_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<_florent_> AndrewD: Nice, I wasn't aware of this open source CAN core (I used one on a project a few years ago with LiteX but it was the commercial one from Xilinx).
<_florent_> This would be interesting to get this core working with LiteX and would be a good demonstration of the use of the GHDL/Yosys VHDL frontend
<_florent_> Once working, we could see how it could eventually integrate the ecosystem of cores or/and where it it's maintained
<_florent_> What kind of issues do you currently have?
<_florent_> If it's related to the integration (ex core integrated but registers not behaving as expected), I would be able to provide feedback
<_florent_> If it's more related to the CAN functionnality itself, it would require more work and we could see how to work together on this
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<_florent_> AndrewD: BTW, I also got this ETA for the Ti60 dev board
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<DerekKozel[m]> _florent_: Writing the *Flash* over PCIe is supported (I have seen this). Is loading the gateware image direct to the FPGA (?partial reconfig?) over PCIe supported (No write to the external Flash)
<_florent_> DerekKozel[m]: not currently no, but partial reconfig over PCIe should be possible with: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/icap.py#L268-L325
<DerekKozel[m]> Ok! That's what I thought the current functionality was at. I know the flash has a lot of write cycles, but *shrug*. Also the dual boot feature of the bootloader is very cool. Thank you again for making such a great project
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<AndrewD> _florent_: the CAN core is integrated but "dead" - wishbone reads return 0. My gut feel is that this is something I got wrong with GHDL. I also have a litex simulation but it generates a file that gtkware is not happy with for the CAN registers so I'm a but stuck... I'll push a tree and let you know when it is done.
<AndrewD> _florent_:  I also have device tree integration for linux on litex and the linux CAN driver integrated into buildroot: I expected the CAN core to "just work" :)