_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<tnt> Mmm ... I have a test design where if I build with pcie_x8 gen 3 and 256b data width, then /litepcie_util dma_test just hangs and doesn't do anything.
<tnt> But if built with pcie_x4 gen 3 and 128b data width, it works fine.
<tnt> Note that in both cases, the board is recognized and shows up in lspci and the 'info' and 'scratch_test' command seem to work just fine.
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<_florent_> tnt: Are you also passing the 256b data_width to the PHY wrapper? ex: https://github.com/enjoy-digital/litepcie/blob/master/examples/kcu105.py#L68
<tnt> _florent_: "Also" ? I am just passing it there.
<tpb> Title: self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pc - Pastebin.com (at pastebin.com)
<tnt> I'm still using the add_pcie wrapper, no custom endpoints yet.
<_florent_> ok, so this is similar to the configuration that was tested, strange
<tnt> sys_clk is 125 MHz rather than 200 MHz, not sure if that's an issue.
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<_florent_> that could be worth doing a test with a higher sys_clk yes, the PCIe side is running at 256-bit/250MHz, so 2X the sys_clk, the issue could be in the CDC
<tnt> Trying that now. Not sure if the DDR4 can do 4*200 MHz though.
<_florent_> At 200MHz, Vivado will probably complains about the max BUFG frequency, maybe just try at first 150MHz, which will already reduce the CDC ratio below 2
<tnt> ... I did echo 1 > remove on the nvme root drive instead of the xilinx card ...
<tnt> Now how do you reboot a remove machine without the 'reboot' command ? :/
<tnt> Got it :) "echo b > /proc/sysrq-trigger"
<tnt> _florent_: no luck, still same behavior :/
<_florent_> tnt: ok, not sure I understand why this is not working. One thing you can also try is to stay in gen3 X4 but set data_width=256 on the PHY. 128-bit <> 256-bit adapters will be inserted in the PHY wrapper and this should be optimal with your 125MHz clock (just able to saturate the link).
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<jersey99> Hello Litex .. I am having some problem booting code from a bootrom at a certain address (following instructions at the top of the page https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU). I managed to boot the same code via serialboot just fine. I do get the "Liftoff!" message, as I type "boot 0x20000000", and the actual boot
<jersey99> never seems to happen. Any ideas?
<tnt> _florent_: mmm, trying in x4 with width=256 locked up the whole machine when trying to load the litepcie.ko module. (and ended this debug session until I can get someone local to reboot it ...)
<_florent_> tnt: sorry... I could try re-do a test with a similar configuration in the next days (but don't think the code has changed in this since last test)
<_florent_> jersey99: I could have a look if you can provide a minimal repro
<tnt> _florent_: which vivado version are yo uusing btw ? I'm at 2021.2 now. I also did have to update the .xci to use the right Quad. But I made the same change to the x8 as I made to x4 and that seemed to work fine.
<tnt> But I might wait until I have a card locally for further pcie test to avoid the crash and move on to try and get the JESD link up. I was busy last month with other stuff but picking up where I left of last time
<tnt> and x4 bw is enough anyway for now. The x8 was mosty just to make sure it worked.
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<_florent_> tnt: BTW, not sure which version of LitePCIe you are using, but make sure you have this applied in the PHY wrapper:
<_florent_> the issue was only triggering on servers, the fields does not seem to be check on regular PC
<_florent_> but yes, for this kind of work, being able to work on the hardware locally will be a lot easier
<tnt> _florent_: yup it's applied. I just did a full --update this morning before resuming work.
<tnt> _florent_: btw, is there any examples for JESD ?
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<_florent_> tnt: I'll add one example to the repo or will share one
<tnt> _florent_: tx :)
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