Hi, does liteeth 1G rgmii have support for Altera/Intel? I didn't see any examples in liteeth nor Altera/Intel boards in litex-boards.
AndrewD: Ok, if that's related to the wishbone, it should not be too complicated to debug. It would also be that LiteX use word addressing on the wishbone bus and the core is expecting byte addressing and address would need to be shifted.
Hello, total noob here. I'm trying to add a custom, simple wishbone slave peripheral (Verilog) on the Arty A7, using VexRiscV, but the SoC BIOS does not start up when my module is instantiated. The corresponding Verilog code is "wrapped" in a module(Module, AutoCSR), in which I create a wishbone.Interface(data_width=32, adr_width=32) and map the
wishbone pins in module.specials. This seems to work technically, at least Vivado does not complain. However, I'm unsure how do I correctly instantiate this module in the platform code, how does it play with the memory map, CSR, etc. Are there examples how to do that? Thanks!
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jevinskie[m]: nice, would you like to contribute it?
jevinskie[m]: hmm, <email@example.com>, strange I don't remember creating this email address :)
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ejcspii: Could you eventually share a minimal example of your issue?
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Yeah I’ll try and get my various changes extricated from each other and submit PRs :)