06:26 <shaynal> Hi, does liteeth 1G rgmii have support for Altera/Intel? I didn't see any examples in liteeth nor Altera/Intel boards in litex-boards.

06:32 <_florent_> AndrewD: Ok, if that's related to the wishbone, it should not be too complicated to debug. It would also be that LiteX use word addressing on the wishbone bus and the core is expecting byte addressing and address would need to be shifted.

06:32 <_florent_> AndrewD: like it's done here for example: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/eos_s3/core.py#L79

06:32 <_florent_> AndrewD: this is something we should change in LiteX (or at least provide an option to use bytes addressing)

06:33 <_florent_> AndrewD: if this is your issue, it will be another good reason to do it :)

06:33 <_florent_> AndrewD: I'll try to look at the code you shared

06:35 <_florent_> Hi @shaynal, I'm indeed not sure LiteEth has a RGMII PHY on Altera/Intel devices, but the approach should be really similar to the one used on Xilinx/Lattice devices

06:36 <_florent_> Happy to guide you or provide the skeleton/tell you how to simply verify it's working.

06:37 <_florent_> I can also look to see if I have an Altera/Intel board with 1Gbps RGMII and could do some tests

18:49 <jevinskie[m]> <shaynal> "Hi, does liteeth 1G rgmii have..." <- I think I got this into a working state the last time I worked on it a few months ago. Let me know if you have any questions! https://gist.github.com/jevinskie/b186bb08b2b60ad7dda54982c5b5d15a

21:02 <ejcspii> Hello, total noob here. I'm trying to add a custom, simple wishbone slave peripheral (Verilog) on the Arty A7, using VexRiscV, but the SoC BIOS does not start up when my module is instantiated. The corresponding Verilog code is "wrapped" in a module(Module, AutoCSR), in which I create a wishbone.Interface(data_width=32, adr_width=32) and map the

21:02 <ejcspii> wishbone pins in module.specials. This seems to work technically, at least Vivado does not complain. However, I'm unsure how do I correctly instantiate this module in the platform code, how does it play with the memory map, CSR, etc. Are there examples how to do that? Thanks!

21:30 <_florent_> jevinskie[m]: nice, would you like to contribute it?

21:31 <_florent_> jevinskie[m]: hmm, <jevinsweval@gmail.com>, strange I don't remember creating this email address :)

21:33 <_florent_> ejcspii: Could you eventually share a minimal example of your issue?

22:56 <jevinskie[m]> Yeah I’ll try and get my various changes extricated from each other and submit PRs :)