_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
tpb has quit [Read error: Connection reset by peer]
tpb has joined #litex
acathla has quit [Quit: [Guru Meditation]]
acathla has joined #litex
C-Man has joined #litex
peepsalot has joined #litex
peeps[zen] has quit [Ping timeout: 260 seconds]
peeps[zen] has joined #litex
peepsalot has quit [Ping timeout: 260 seconds]
Degi has quit [Ping timeout: 258 seconds]
Degi has joined #litex
peepsalot has joined #litex
peeps[zen] has quit [Ping timeout: 260 seconds]
tucanae47_ has quit [Ping timeout: 264 seconds]
sorear has quit [Ping timeout: 264 seconds]
tucanae47_ has joined #litex
sorear has joined #litex
_florent_ has quit [Read error: Connection reset by peer]
_florent_ has joined #litex
FabM has joined #litex
FabM has quit [Changing host]
FabM has joined #litex
linear_cannon has quit [Read error: Connection reset by peer]
linear_cannon has joined #litex
linearcannon has joined #litex
linear_cannon has quit [Killed (NickServ (GHOST command used by linearcannon!~linear_ca@50.35.78.163))]
linearcannon is now known as linear_cannon
TMM_ has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM_ has joined #litex
<Melkhior> 'lo
<Melkhior> _florent_: trying to figure out a bug that I have, and I just saw this commment: https://github.com/enjoy-digital/litex/blob/70c5be6fb848d20cd20b590a69b246aad2092b24/litex/soc/interconnect/wishbone.py#L166
<Melkhior> what does it mean? It seems the 'register' parameter is True by default for SoC (https://github.com/enjoy-digital/litex/blob/70c5be6fb848d20cd20b590a69b246aad2092b24/litex/soc/integration/soc.py#L1014)
<Melkhior> so I'm guessing it doesn't break that much :-)
<Melkhior> TIA
<Melkhior> (my design had a SBus -> Wishbone bridge, and occasionally my bridge returns a 'rerun' because it didn't receive a Wishbone ACK in time ; limit is 50 SBus cycles, or about 200 Wishbone cycles...)
<Melkhior> (in about 0.5-2% of read accesses)
FabM has quit [Ping timeout: 268 seconds]
cr1901 has quit [Quit: Leaving.]
cr1901 has joined #litex
peeps[zen] has joined #litex
peepsalot has quit [Ping timeout: 264 seconds]
jersey99 has joined #litex
peepsalot has joined #litex
peeps[zen] has quit [Ping timeout: 268 seconds]
indy has quit [Remote host closed the connection]
indy has joined #litex
mithro has quit [Ping timeout: 244 seconds]
mithro has joined #litex
zyp has quit [Ping timeout: 244 seconds]
zyp has joined #litex
alanvgreen_ has joined #litex
guan_ has joined #litex
alanvgreen has quit [*.net *.split]
guan has quit [*.net *.split]
alanvgreen_ is now known as alanvgreen
guan_ is now known as guan
<jersey99> Thanks sajattack[m]
<jersey99> I agree that it is super slow.
<jersey99> Another noob question: When using a litedram core, the default firmware/cpu code that gets loaded into the bios to run the dram calibration doesn't execute (essentially the bios doesn't boot) until I explicitly open the terminal. Is this intentional? If so, how to have it run automatically with a timer, say?
TMM_ has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM_ has joined #litex
<cr1901> The BIOS code waiting for you to open a terminal sounds specifically like a USB serial thing. If you are using a plain old UART, Idk what could be wrong
<tpw_rules> i think the jtag uart has a buffer full flag the BIOS can spin on
shenki has quit [Ping timeout: 260 seconds]
shenki has joined #litex