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<shenki>
_florent_: thanks for the suggestions
<shenki>
_florent_: the sim worked fine with the toolchain I was using (Debian's cross compiler)
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<shenki>
_florent_: but the fpga needed the buildroot toolchain. with that the bios worked for me
<shenki>
_florent_: i'll do some investigation as to why that is
<_florent_>
shenki: Thanks, that's strange to observe a difference between the simulation and the board on this. If you find something please let us know
<_florent_>
somlo: For mor1kx, I'll have a look tomorrow on my dev machine
<_florent_>
somlo: but there is indeed probably something wrong with the duplicate gcc_triple attribute/method
<_florent_>
thanks to navan93 we now also have a CI test of the different RISC-V CPUs, I'll also try to spend time to also enable it for Microwatt/LM32/Mork1x. This will also be a way to ensure we provide valid toolchains for these CPUs.
<cr1901>
_florent_: I've been thinking more re: the litex build... what I actually want is not necessarily meson support, but more parallelism when building picolibc with the rest of litex. The software is now 1000+ files to compile from a clean build! 1/2
<cr1901>
As a compromise, would you accept a feature for (s)ccache support?
<cr1901>
I already tried it locally/it works, it's not many lines. But if you want to override, that's fine too
<_florent_>
cr1901: If you already have a proof of concept for this, I would be happy to review it/test it
<cr1901>
_florent_: Okay lemme make the proof of concept applicable to besides my machine only :)
<cr1901>
_florent_: Strangely sccache is slower on my machine, but the PR works. I think management engine doesn't like the riscv toolchain. Attempting more tests