<lofty>
[04:57:16] Myrl-saki: I need to learn how PIPs work! <--- there's not much to learn; a Programmable Interconnect Point connects one wire to another
<Myrl-saki>
Oh yeah, I get that part. What I'm curious about is for example, how signals get from (R,C) to (R',C')
<Myrl-saki>
And also how things get connected uh, from external signals? to the slices?
<Myrl-saki>
I guess what I'm saying is I'm curious about the topology here. If for example, I want to create a D latch, I think it's possible for a LUT to feedback to itself, and put an enable pin. How does it do that?
bpye has quit [Ping timeout: 245 seconds]
<lofty>
Myrl-saki: the LUT will have an output signal in the SLICE; PIPs will connect it to some wires, which are arranged in a grid shape - I think you're using Gowin, so it would be the X1 wires.
bpye has joined #yosys
<lofty>
At the end of each wire is a switch box made up of PIPs to connect more wires together, which is how it makes the turns needed to end up back at the inputs of the slice
<lofty>
And then a connection box made up of PIPs is used to pull wire signals into slice inputs
<Myrl-saki>
Ahhh thanks. And I'm guessing the router's job is to figure out which PIPs to enable?
<Myrl-saki>
Huh yeah, I think I see.
<Myrl-saki>
Oh wait, am I slightly wrong on that?
<lofty>
Myrl-saki: yeah, basically.
daglem has joined #yosys
<Myrl-saki>
I think I see it now by the way! :) Specifically the "turns needed to end up back" part.
<Myrl-saki>
This seems like it enables PIPs to route one wire to another within a tile.
FabM has joined #yosys
FabM has joined #yosys
schaeg has joined #yosys
<Myrl-saki>
Hm, how do higher-width MUXes get generated? $pmux?
<Myrl-saki>
I guess pmuxtree also to some extent.
<Myrl-saki>
Oh, muxcover?
<Myrl-saki>
Ah found it.
<Myrl-saki>
Hmmm
<Myrl-saki>
I'll probably need help from someone to understand the timings.
<Myrl-saki>
Oh cool, turns out there are mux tests!
<Myrl-saki>
Hehe. :)
<Myrl-saki>
I'll push this in a bit I think.
xiretza[cis] has quit [Quit: Idle timeout reached: 172800s]
<lofty>
povik: what did you change in toymap? it's not too obvious from the commit history.
<Myrl-saki>
Info: Max frequency for clock 'sysclk': 29.71 MHz (PASS at 24.00 MHz)
<Myrl-saki>
oh no what have I done
<Myrl-saki>
Hm, what does shiftx do
<Myrl-saki>
Or rather, how does shiftx get transformed as passes run?
schaeg has quit [Quit: Konversation terminated!]
schaeg has joined #yosys
keesj has joined #yosys
<keesj>
Hi, I am wondering about the compressed instruction set option of PicoRV32. Does COMPRESSED_ISA =1 imply a choice between the normal and compressed set or should is be seen as addition?
<Myrl-saki>
Draft for 2 reasons: (a) I'm not sure if the timings are right (b) I have no idea how to integrate it with synth_gowin.
<Myrl-saki>
I took the timings based on LUT5 and LUT6.
<keesj>
tnt: thanks (that is what GPT was also saying but I wanted to double check)
<lofty>
keesj: are you actually trusting GPT on...*anything?*
<keesj>
Pretty much yes, trust but verify
ppisati has quit [Remote host closed the connection]
<Myrl-saki>
Seems like there's actually a pass to convert LUTs back to MUXes. I'm not sure when it actually triggers though.
<Myrl-saki>
Okay, so I think the reason why I need to set a proper cost is because Yosys might decide to promote a 3-input mux into a 4-input mux?
<Myrl-saki>
Hm
<lofty>
Myrl-saki: there's basically no reason to use lut2mux though
<Myrl-saki>
I checked and even before this patch, synth_gowin seems to know how to convert a MUX4 to a 2xLUT3 + MUX2 sometimes.
<Myrl-saki>
And I'm not sure how it does it lol
<Myrl-saki>
Oh wait.
<Myrl-saki>
Ah.
<Myrl-saki>
I think this was a misinterpretation on my part.
<Myrl-saki>
I think what muxtree is comparing is then whether to use a LUT5 or a MUX4.
<Myrl-saki>
Errr muxcover
<Myrl-saki>
Yeah, okay, cool.
<Myrl-saki>
In hindsight though, yeah, turns out I could have just implemented this with a LUT5 lol
schaeg has quit [Ping timeout: 246 seconds]
FabM has quit [Ping timeout: 255 seconds]
<povik>
lofty: lutrewrite generalizations are the improvement
<povik>
it considers more structures to rewrite the network into (different LUT sizes and also what some of the literature calls a 'shared' variable)
<povik>
also rewriting got enabled for LUT6 mapping
<povik>
Myrl-saki: so, about that PR, very curious
<povik>
does that demonstrably improve QoR?
<povik>
wouldn't the MUX gates like that, being only an optimized composition of other technology gates, but being registered for a mapping target of its own anyway, be called a 'supergate' in the literature?
<lofty>
Well, ABC9 can't directly map to this anyway, so