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Myrl-saki>
How do I use external, er, libraries? Do I just put it as a Git submodule, and add it to read_Verilog?
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lofty>
Myrl-saki: they're just files to Yosys
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Myrl-saki>
Yep, just to clarify. I'm asking for what's "usually done" since this is my first project.
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tnt>
Myrl-saki: yeah submodules is a good way imho.
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Myrl-saki>
I just thought of something and wonder if Yosys implements this.
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Myrl-saki>
Maybe with splitnets?
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tnt>
I mean, it should implementi it just fine but if it's supposed to be a UART RX ... it'll be big ...
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Myrl-saki>
The idea that I had was that this basically works as a demuxer, so the input side doesn't have to be treated anymore.
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Myrl-saki>
While the current implementation seems to be using a mask. (x & mask | y & ~mask)
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