whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<Myrl-saki> How do I use external, er, libraries? Do I just put it as a Git submodule, and add it to read_Verilog?
<lofty> Myrl-saki: they're just files to Yosys
<Myrl-saki> Yep, just to clarify. I'm asking for what's "usually done" since this is my first project.
<tnt> Myrl-saki: yeah submodules is a good way imho.
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<Myrl-saki> I just thought of something and wonder if Yosys implements this.
<Myrl-saki> Maybe with splitnets?
<Myrl-saki> o
<Myrl-saki> Huh.
<tnt> I mean, it should implementi it just fine but if it's supposed to be a UART RX ... it'll be big ...
<Myrl-saki> The idea that I had was that this basically works as a demuxer, so the input side doesn't have to be treated anymore.
<Myrl-saki> While the current implementation seems to be using a mask. (x & mask | y & ~mask)
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