<Myrl-saki>
Just had a thought, assuming you're making a shifter using LUTs as MUXes, assuming MUX2, it's probably a good idea to switch the MUX cases every layer, because it decreases the tail latency.
<Myrl-saki>
s/switch/swap/
<Myrl-saki>
Take 2 latencies, L1 and L2, such that L2 > L1, assume that the "shift" MUX takes L2, then an all-shift would be n*L2, while a no-shift would be n*L1. Ideally, it should be n*(L1 + L2)/2 for both.
<povik>
> On each benchmark LUT4 and LUT6 mappings are attempted, once with ABC, once with toymap, and once with toymap after ABC preprocessed the AIG (labeled abc+toymap)
<povik>
AIG being the and-inverter graph
<povik>
so you reap the benefits of general logic optimizations done by ABC, but don't let it do the mapping itself