whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<Myrl-saki> Okay, I have one of the weirdest problems, I'll check if I can get an MRE.
<Myrl-saki> L17-19 seems to result in a race condition.
<Myrl-saki> If I add an unrelated write, the unrelated write commits, but that one doesn't.
<Myrl-saki> If I choose it to be `2, 3:` instead of `default:` it also works.
<Myrl-saki> `decoder_mem_width` is `[1:0]`.
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<Myrl-saki> Turns out input cones are really useful. :)
<Myrl-saki> Like, the input cone selector
<Myrl-saki> (Okay, turns out I misinterpreted something, and it was just actually unused wires.)
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