whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<Myrl-saki> How fast are the interconnects in other architectures? Seems like my design is mostly limited by routing.
<killjoy> ^ says everyone doing FPGA development ever.
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<Myrl-saki> Hi, can someone review this please? I also added a description for the rationale. https://github.com/YosysHQ/yosys/pull/4000
<Myrl-saki> I just realized that this is probably not a full fix, as `$add` and `$sub` won't be able to unify with `share -aggressive` maybe.
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<Myrl-saki> But for now, I think solving the `$lt` family is good enough.
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