whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
tpb has quit [Remote host closed the connection]
tpb has joined #yosys
shoragan has quit [Quit: quit]
shoragan has joined #yosys
lexano has quit [Ping timeout: 240 seconds]
shoragan has quit [Read error: Connection reset by peer]
shoragan has joined #yosys
somlo has quit [Remote host closed the connection]
somlo has joined #yosys
<Myrl-saki> How do I make $lsl/$lsr not take 50% of my design? lol
<tnt> Myrl-saki: you need hardware multiplier for that :)
<tnt> How wide is the datapath ?
<Myrl-saki> 32-bit, and yes! I'm actually considering figuring out how to get DSP block to work for Gowin lol
<Myrl-saki> I think it's because Yosys is hyperoptimizing for latency, but I don't think it's even needed.
<tnt> Shoudl be ... ~224 LUT4s if my math is correct.
<Myrl-saki> I used to be able to use LUT4 for the shifters only, and use any LUTs everywhere elses.
<Myrl-saki> But now, even if I techmap to abc it, it gets relutted(?) later.
<Myrl-saki> I guess I could just not use synth_gowin?
Myrl-saki has left #yosys [WeeChat 4.0.2]
Miyu-saki has joined #yosys
Miyu-saki is now known as Myrl-saki
<Myrl-saki> Ah whoops
<Myrl-saki> So I did spam, sorry.
<Myrl-saki> Meant to send this instead.
<Myrl-saki> MUX2_LUT5 477
<Myrl-saki> MUX2_LUT6 221
<Myrl-saki> MUX2_LUT7 69
Myrl-saki has left #yosys [#yosys]
Myrl-saki has joined #yosys
<Myrl-saki> Huh weird.
<lofty> [08:21:42] Myrl-saki: I think it's because Yosys is hyperoptimizing for latency, but I don't think it's even needed. <--- actually no, it's really not
<Myrl-saki> I think Weechat's broken lol
<lofty> Yosys turns multiplies into shift-and-add, which is generally the fastest way to map them on modern FPGAs without DSPs
<Myrl-saki> This is taking 50% of my design
<Myrl-saki> 25% each shifter, I'm guessing.
<Myrl-saki> Hmm
<tnt> Usually you would only use one shifter. And then reverse the bits at the input/output of it. Less costly than 2 full shifters.
<Myrl-saki> Oh yeah, that's true.
<lofty> Yeah, one transforms left shifts into right shifts and back again
<Myrl-saki> Thanks, how about the asr/lsr toggling?
<lofty> If your shifter takes in the bits to fill, then for ASR it's the sign bit, and for LSR it's zero
<Myrl-saki> I'm just using `>>` and >>>`. I'm guessing `opt` will just be able to figure out to merge them?
<lofty> eeeh
<lofty> I don't know, actually.
<Myrl-saki> Thanks. :) FIgured something out I think.
philtor has quit [Ping timeout: 240 seconds]
ec has quit [Remote host closed the connection]
ec has joined #yosys
philtor has joined #yosys
lexano has joined #yosys
ZipCPU_ has joined #yosys
tux3_ has joined #yosys
ZipCPU has quit [Remote host closed the connection]
tux3 has quit [Quit: ZNC 1.8.2 - https://znc.in]
ZipCPU_ is now known as ZipCPU
smkz has quit [Quit: smkz]
smkz has joined #yosys
bjorkintosh has quit [Ping timeout: 248 seconds]
bjorkintosh has joined #yosys
bjorkintosh has quit [Changing host]
bjorkintosh has joined #yosys
derekn has quit [Ping timeout: 272 seconds]
derekn has joined #yosys
bjorkintosh has quit [Quit: Leaving]
bjorkintosh has joined #yosys
bjorkintosh has quit [Changing host]
bjorkintosh has joined #yosys
nonchip has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
nonchip has joined #yosys