whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<Myrl-saki> I uh
<Myrl-saki> Turns out >LUT4s was what's been killing my cell usage?
<Myrl-saki> I enabled nowidelut, and everything is much better.
<Myrl-saki> I am so confused.
<Myrl-saki> Like, it's the difference between 2000 and 4000 LUTs.
<Myrl-saki> And I see a lot of LUT1s. I'm guessing these are inverters?
<Myrl-saki> Or are they, erm, repeaters?
<lofty> Myrl-saki: they're inverters. Have you considered synth_gowin -abc9?
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<corecode> Myrl-saki: do you write tests?
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<Myrl-saki> corecode: Not yet, but I've been making more simulation code.
<Myrl-saki> ERROR: Module 'DFFC' with (* abc9_box *) has no timing (and thus no connectivity) information.
<Myrl-saki> lofty:
<Myrl-saki> Hmm
<lofty> Um. What's your Yosys version?
<lofty> Oh, right, I see the issue
<Myrl-saki> Should be the latest.
<Myrl-saki> Ah, should these be abc9_flop?
<lofty> No
<lofty> These don't fit the model of abc9_flop
<lofty> However
<lofty> abc9_box describes something combinational
<lofty> and a certain past somebody seems to have written them as sequential paths instead
<lofty> >.>
<Myrl-saki> Hm, now I'm slightly curious what's causing the DFFC though. Maybe it's my initialization?
<Myrl-saki> I don't think I'm using asynchronous clear anywhere
<lofty> are you using asynchronous set?
<Myrl-saki> I don't *think* so. I'll try to see if I can figure out why.
<Myrl-saki> Ah, I think it's just the fact that cells_sim.v gets loaded?
<Myrl-saki> Oh hm
<Myrl-saki> Thanks. :)
<Myrl-saki> :o
<Myrl-saki> wow
<Myrl-saki> So it's halfway between nowidelut and abc widelut.
<Myrl-saki> Thanks. :)
<lofty> Which gives you the performance of ABC widelut (better, actually), while being noticeably less area
<Myrl-saki> Yep! Because of routing and whatnot, right?
<Myrl-saki> Thansk so much. ^^
<lofty> Myrl-saki: no, because of whiteboxes (and because of delay information)
<Myrl-saki> Ah
<Myrl-saki> Because it actually knows more granular timings?
<Myrl-saki> I read your post and abc works on unit delays?
<lofty> yep
<lofty> So a LUT8, a LUT4, and a LUT2 have equal delay :p
<lofty> Obviously, given that a LUT2 can use the fastest inputs of a LUT4, and a LUT8 needs to go through a LUT4 and 4 layers of muxes
<lofty> this isn't in the least bit realistic :p
<Myrl-saki> Also, TIL about this: `Obviously, given that a LUT2 can use the fastest inputs of a LUT4` how does this work? I'm guessing it's decoder delay or something? Since LUT4s are basically 16-bit SRAMs, right?
<lofty> They are, yes; where there's a mux tree to turn the 16 config bits into the 1 output bit
<lofty> so the four inputs correspond to the four mux layers needed
<lofty> and so the inputs will have differing propagation delay based on the number of mux layers that the signal has to go through
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<Guest32> hello, is there a way to read environment variables from a native yosys synth script, or is TCL the only way to go here?
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<ZipCPU> Perhaps you can read environment variables from an embedded Python script? That would make sense.
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<jleightcap> I have a circuit that's entirely combinational, and as I try to compile larger and larger versions, ABC takes a very long time
<jleightcap> Is there any substitute that isn't as single-threaded?
<jleightcap> I'm attempting `abc -fast` now, but without I stopped it after about 30 hours
<jleightcap> Just `abc`, that is, so maybe `-fast` will be much better. Just waiting now.
<lofty> jleightcap: no, presently not.
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