whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<Myrl-saki> How do I directly use $alu in my code?
<lofty> Myrl-saki: you don't.
<lofty> Okay, sure, you can instantiate it as \$alu, but saying "I need to instantiate a Yosys cell" outside of Yosys itself is a pretty strong X/Y problem
<lofty> The job of `alumacc` is to lower things to $alu cells as needed to make them fast
<Myrl-saki> Yep, that's true. I'm pretty sure this can be unified into a single ALU but I can't seem to make Yosys do it.
<tnt> What's the target fpga ?
<lofty> Myrl-saki: no, that can't be turned into a single ALU.
<Myrl-saki> (Just to clarify, `unsigned_compare` should be `'x` there, in hindsight.
<Myrl-saki> For the '0 cases.
<Myrl-saki> tnt: Right now I'm targeting Gowin/Tang Nano 9k.
<Myrl-saki> Okay, so I was able to skip the `and` gate by using the 'x.
<Myrl-saki> Ah.
<Myrl-saki> I think I understand what you mean by can't be a single ALU now.
<Myrl-saki> Hm
<lofty> ...I think I also just noticed a flaw in `synth_gowin` which does not help
<Myrl-saki> I'm guessing that there's parameters which `show` doesn't show.
<Myrl-saki> This is what it generates when I use `$signed(ra) < $signed(rb)` instead.
<Myrl-saki> Which makes me think that maybe Yosys could merge them, because I can just replace `1` with `mode`, because it's only valid when `mode` is 1.
<lofty> If you run `write_verilog` in a shell when stepping through commands you can get a reasonable idea of what Yosys is thinking
<Myrl-saki> Oohh thanks. I think it's really just the signedness difference. Hmm.
<Myrl-saki> `if (node->is_signed == is_signed && node->invert_b && node->c == State::S1)`
<Myrl-saki> I wonder if this is actually required.
<Myrl-saki> I mean, it's also not trivial to just change the checks.
<lofty> Easiest way to answer that is to remove it and then run the Yosys test suite
<Myrl-saki> Thanks. I'll do that. It'd be nice to make a PR if I figure this out.
<Myrl-saki> Yay. :)
<Myrl-saki> I don't think there are tests in place to catch this yet. How do I name the test? https://github.com/YosysHQ/yosys/pull/3991
<Myrl-saki> Okay there for sure aren't tests, because turns out something's wrong with this. :(
<Myrl-saki> How it looks now. :) https://i.imgur.com/e4C8qbs.png
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