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<Myrl-saki>
How do I directly use $alu in my code?
<lofty>
Myrl-saki: you don't.
<lofty>
Okay, sure, you can instantiate it as \$alu, but saying "I need to instantiate a Yosys cell" outside of Yosys itself is a pretty strong X/Y problem
<lofty>
The job of `alumacc` is to lower things to $alu cells as needed to make them fast
<Myrl-saki>
Yep, that's true. I'm pretty sure this can be unified into a single ALU but I can't seem to make Yosys do it.
<Myrl-saki>
This is what it generates when I use `$signed(ra) < $signed(rb)` instead.
<Myrl-saki>
Which makes me think that maybe Yosys could merge them, because I can just replace `1` with `mode`, because it's only valid when `mode` is 1.
<lofty>
If you run `write_verilog` in a shell when stepping through commands you can get a reasonable idea of what Yosys is thinking
<Myrl-saki>
Oohh thanks. I think it's really just the signedness difference. Hmm.