whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<FL4SHK> can yosys be made to use multiple CPU cores?
<FL4SHK> I have 16 hardware threads... hoping to speed up the process
<FL4SHK> (8 actual CPU cores)
<tnt> FL4SHK: nope
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<FL4SHK> tnt: that's unfortunate
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<tnt> But how long can the synthesis be ? What are you doing ?
<FL4SHK> I mean it takes a while because of how large my module is
<tnt> yeah, but define what you consider "a while" and "how large" (which target ?)
<FL4SHK> I'm only using yosys to try to get better results than Vivado
<FL4SHK> the "target" is defined in Vivado
<FL4SHK> it's an Arty A7 100T
<FL4SHK> the number of lines of code is 100k but a lot of it is because it's generated by SpinalHDL
<tnt> Mmm, ok, I see.
<FL4SHK> okay this idea doesn't seem to be something that will work
<FL4SHK> since even NeoVim can't open the synthesized .v file
<FL4SHK> not with `proc` involved
<FL4SHK> I'll try just `synth`
<FL4SHK> what I'm hoping to achieve here is test whether yosys can figure out that I'm really doing a synchronous read from an array
<FL4SHK> I am doing an asynchronous read from an array and passing the data to a pipeline skid buffer
<FL4SHK> I was hoping yosys would be able to figure it out since Vivado doesn't
<FL4SHK> otherwise I'll have to write fancier code that directly does synchronous reads from the array
<FL4SHK> ...my goal is to infer BRAM
<FL4SHK> since these arrays are rather large
<FL4SHK> what I've made is a GPU for 2D graphics
<FL4SHK> sprites and backgrounds
<FL4SHK> very configurable and also open source
<FL4SHK> it's in my libcheesevoyage library on my Githbu
<FL4SHK> GitHub
<FL4SHK> in the `hw/spinal/libcheesevoyage/gfx` directory
<FL4SHK> my GitHub username is the same as my username here on IRC
<FL4SHK> "fl4shk"
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<Guest12> anyone know how to simulate a verilog in yosys?
<FL4SHK> Guest12: yosys isn't a simulator
<FL4SHK> you need something like Verilator or Icarus Verilog for that
<FL4SHK> also, for my problem, I have determined that yosys won't work for my situation
<FL4SHK> so I'm going to implement something else
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<Guest12> FL4SHK then what's the point of yosys if verilator/icarus can directly simulate verilog?
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<whitequark[cis]> synthesis
<whitequark[cis]> that said, yosys does have a sim pass
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<FL4SHK> oh it does?
<FL4SHK> oops
<FL4SHK> I forgot about CXX RTL
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<whitequark[cis]> FL4SHK: no, CXXRTL and the `sim` pass are entirely independent
<whitequark[cis]> so Yosys has two simulators in it
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<FL4SHK> whitequark[cis]: gotcha
<FL4SHK> that's very cool
<FL4SHK> okay so yosys actually managed to synth_xilinx my feeding pipeline skid buffers with asynchronous reads to BRAM
<FL4SHK> I had to use `synth_xilinx` for it
<whitequark[cis]> what were you using before?
<FL4SHK> Vivado
<FL4SHK> its native synthesis
<whitequark[cis]> ah
<FL4SHK> Now I'm switching flow
<FL4SHK> s
<FL4SHK> this is excellent
<FL4SHK> can I tailor the yosys to target specific Xilinx FPGAs?
<FL4SHK> it appears that it's using UltraScale things
<FL4SHK> but that's not what I have here
<Wanda[cis]> you can choose the target family with `synth_xilinx -family <...>`; choosing specific FPGA is not supported
<Wanda[cis]> it should be using series7 as the target by default
<FL4SHK> family is fine with me
<FL4SHK> oh
<FL4SHK> but it output stuff that's apparently not available in series7
<FL4SHK> I'm working on adjusting my code
<Wanda[cis]> what kind of stuff?
<FL4SHK> RAM64M
<Wanda[cis]> that's a valid 7 series primitive
<FL4SHK> oh I see
<FL4SHK> Xilinx's documentation didn't show it for 7 series
<FL4SHK> Oh wait
<FL4SHK> so it does
<FL4SHK> my mistake!
<Wanda[cis]> hm?
<Wanda[cis]> I'm looking at UG768 (v14.7) and it's right there
<FL4SHK> right
<FL4SHK> I got linked to Ultrascale
<FL4SHK> when I searched
<FL4SHK> in any case
<FL4SHK> that's not a design element I want to use
<FL4SHK> I want to use fully block RAM
<FL4SHK> so I'll be adjusting my code
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