whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<povik> so I went over Andy's PR to create Booth multipliers
<povik> i want to merge it if there aren't any objections, with the promise that I will do a pass over the code after merging to clean it up a little
<povik> Andy seems to have done the changes we requested in Monday's dev call
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<mithro> I'm pretty sure I am doing something obviously wrong, but I'm not quite sure what - I'm getting these "hanging wires and buffers" in my `show` output despite calling `opt_clean` -- SystemVerilog code @ https://pastebin.ubuntu.com/p/tHXb5x2tZQ/ https://usercontent.irccloud-cdn.com/file/N33jSXJN/image.png
<tpb> Title: Ubuntu Pastebin (at pastebin.ubuntu.com)
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