whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<corecode> Myrl-saki: what does this calculation do?
<corecode> Myrl-saki: is this a common way to express this?
<corecode> Myrl-saki: can't you just look at the high bits of the address?
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<Guest99> Is there anything wrong with this verilog code?
<Guest99> It works fine in simulation (icarus) and various linters (verilator, verible)
<Guest99> are happy with it. However, yosys errors during synthesis: registers.v:0:
<Guest99> ERROR: Identifier `\i' is implicitly declared and `default_nettype is set to
<Guest99> none.
<tpb> Title: initial begin integer i; for (i = 0; i < 32; i++) begin memor - Pastebin.com (at pastebin.com)
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<lofty> Guest99: that code by itself looks fine, though perhaps the `integer i` declaration needs to be moved outside the `initial` block?
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<Guest99> lofty: that does fix it, but I wanted to limit to scope of i to avoid accidentally reusing it in a different loop elsewhere in the file. I found a better workaround by extracting the code to a task. It seems like maybe local declarations are not allowed in the always block. But I don't really understand why some tools accept it and others do not.
<gatecat> another workaround is probably to name the block (e.g. `initial begin: foo`)
<gatecat> but this does look like a yosys bug
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