whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<Myrl-saki> Why does yosys create this to scatter the bits for an enable pin? https://i.imgur.com/PzJgMMM.png
<lofty> Myrl-saki: opt_clean -purge and try again :p
<Myrl-saki> Thanks. :) That seems to work for most.
<Myrl-saki> Though, that doesn't seem to be what I needed to fix.
<Myrl-saki> I am getting this diagnostic: `$flatten\furv.$7$memwr$\r$furv.v:126$107_EN[31:0]$365`
<Myrl-saki> Er, sorry.
<Myrl-saki> `Module `top' contains feedback arcs through wires:`
<Myrl-saki> And that's one example of it.
<lofty> I would need more context than that then
<Myrl-saki> Sure thing. I'll push my code.
<lofty> I can't promise I'll take a look at it, given the time
<Myrl-saki> This one has a smaller diagnostic $flatten\furv.$0$memwr$\r$furv.v:125$106_EN[31:0]$135
<Myrl-saki> I'm not so sure what a "feedback arc" means.
<Myrl-saki> FWIW, doing splitnets fixes this.
<Myrl-saki> Ah, I can just splitnets on the modules that have this problem, and thne flatten.
<Myrl-saki> Ah, seems like `share -force` gets it.
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<Myrl-saki> Well, turns out it disappears because it removes the store lol
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<Myrl-saki> jix: Hi, sorry. How exactly do I load the module afetr blackboxing it?
<Myrl-saki> Is this on nextpnr or on yosys?
<Myrl-saki> ERROR: Unable to place cell 'rom', no BELs remaining to implement cell type 'rom'
<jix> Myrl-saki: you load the module into a separate design (see `help design`) and then run techmap with that design as cell library (`help techmap`)
<Myrl-saki> Thanks. :)
<jix> I can elaborate later, but I'm about to leave
<Myrl-saki> Good enough for me. ^^ I just needed a hint.
<jix> Might also be able to just read_verilog the rom.v after synth but I haven't tried that and that gives you less control over what passes to run on that module independent from the rest of the design
<Myrl-saki> Ah! I found a
<Myrl-saki> Yes!
<Myrl-saki> That's exactly what I did. :D
<Myrl-saki> Well kind of. I did it directly before synth, but after all my optimization passes.
<Myrl-saki> Thanks, seems like I got it.
<Myrl-saki> Wild, removing the ROM makes yosys infer block RAM (it says SPX9?). Computers never cease to amaze me. That aside, I think I got it working! :)
<Myrl-saki> Testing in a bit.
<Myrl-saki> Yes!
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<lofty> Myrl-saki: that's a rather peculiar synthesis script
<Myrl-saki> I decided to just flatten and opt, and that produces way smaller than whatever I wrote. : X
<Myrl-saki> 3700 vs 4300
<Myrl-saki> Though, 4300 vs 4700 if I opt without flatten.
<Myrl-saki> With that said, there's probably :tm: bugs in my code, because my core is not responding to UART lol
<Myrl-saki> So that could account for the missing LUTs.
<Myrl-saki> But yeah, so I had an idea of how I wanted the compilation to look in mind, that's why I am compiling each module with their own specific settings.
<Myrl-saki> 92405: Optimizing lut uart.rx_ack_MUX2_LUT5_S0_1_I0_LUT1_F (1 -> 0)
<Myrl-saki> Does this mean it got replaced by a constant?
<Myrl-saki> log(" Optimizing lut %s (%d -> %d)\n", log_id(cell), GetSize(inputs), GetSize(new_inputs));
<Myrl-saki> Seems so :x
<Myrl-saki> Hmm
<Myrl-saki> Can things break from `share`?
<jix> Myrl-saki: Without `-force` it shouldn't break things.
<Myrl-saki> How about -aggressive?
<jix> Myrl-saki: If it does what it says in the help message that shouldn't be able to break things, but it's been a while since I looked at share's source code and I haven't done much with it
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