whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
tpb has quit [Remote host closed the connection]
tpb has joined #yosys
peepsalot has quit [Quit: Connection reset by peep]
peepsalot has joined #yosys
tlwoerner has quit [Quit: Leaving]
tlwoerner has joined #yosys
lumo_e has quit [Quit: Quit]
ec has quit [Read error: Connection reset by peer]
ec has joined #yosys
FabM has joined #yosys
FabM has joined #yosys
notgull has quit [Ping timeout: 255 seconds]
notgull has joined #yosys
<ikskuh> hmm. i have several folders in my project right now. hardware for PCB designs, software for (well doh) software (c/c++ code)
<ikskuh> i wonder how to call the folder which contains the verilog code
<ikskuh> it's not really software, but it also is
<tnt> rtl
<tnt> gw
<tnt> (ie. gateware)
<ikskuh> gateware is nice!
<ikskuh> thanks, i guess i have to adopt gateware now into my dictionar
kraiskil has joined #yosys
kraiskil has quit [Remote host closed the connection]
cr1901 has quit [Read error: Connection reset by peer]
cr1901 has joined #yosys
DoubleJ has quit [Quit: Not all those who wander are lost]
DoubleJ has joined #yosys
DoubleJ has quit [Quit: Not all those who wander are lost]
DoubleJ has joined #yosys
citypw has joined #yosys
citypw has quit [Ping timeout: 256 seconds]
cr1901 has quit [Read error: Connection reset by peer]
cr1901 has joined #yosys
cr1901_ has joined #yosys
cr1901 has quit [Ping timeout: 272 seconds]
cr1901_ is now known as cr1901
<Myrl-saki> Is it weird to see a programmatic approach to setting values? i.e. `x = a; if (p) x = b; if (q) x = c;`?
xiretza[cis] has joined #yosys
<xiretza[cis]> no, allowing to write things out sequentially instead of structurally is exactly what HDLs are for
FabM has quit [Ping timeout: 240 seconds]
<somlo> I like to think about it in terms of "connecting things" rather than "setting values": If you see something like `x = foo ? a : b` then think of a mux with inputs a and b, output x, and selector foo
<somlo> they're connected to each other that way, not "assigned" :)
notgull has quit [Ping timeout: 245 seconds]
notgull has joined #yosys
<xiretza[cis]> <somlo> "I like to think about it in..." <- yes, that's a very structural view, you're basically just plopping down a MUX - processes allow you to write seemingly sequential code instead
DoubleJ has quit [Quit: Not all those who wander are lost]
DoubleJ has joined #yosys
derekn has quit [Ping timeout: 264 seconds]
derekn has joined #yosys
srk_ has joined #yosys
srk has quit [Ping timeout: 272 seconds]
srk_ is now known as srk
nonchip has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
nonchip has joined #yosys
lumo_e has joined #yosys
DoubleJ has quit [Quit: Not all those who wander are lost]
DoubleJ has joined #yosys