<kof123>
"communism implies no state" the people are the state -- america/enlightenment. ignoring whether that is still true or not...conway's law always in effect lol we have corporations nowadays too. point: corporatism fulfills this perfectly, there needs to be some other criteria for most ppl to jump to that
<kof123>
i am the state i am the revolution we are the state it is just memes all the way down
<kof123>
lack of conway's law has made a mess in all these areas, not just code lol
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<kof123>
"the people are the state" and this was going plural: everyone "king" + "pope" jointly -- so "state" got redefined there as well
<kof123>
it is like operator overloading run amok
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* kof123
motions to introduce type checking and semantic versioning, the "confusion of tongues is eternal" bill
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<moon-child>
hmmmmm so question
<moon-child>
could I connect the pcie slots of two computers directly and have them communicate with each other that way?
<moon-child>
or does that fundamentally not work for some reason?
<clever>
generally not
<clever>
a pcie interface is either host or device mode
<clever>
much like usb
<moon-child>
I know it's workable with ethernet--some random exponential backoff where they figure out who's who
<moon-child>
clever: I see
<clever>
but there are some exceptions
<clever>
ive heard that one cpu, had 128 lanes of pcie, that could be freely allocated to pcie slots
<clever>
but, you can also shove 2 of those cpus onto a single motherboard, and cross-wire 64 lanes between the 2 cpu's
<clever>
and then each cpu has 64 lanes free for pcie slots
<clever>
and with an internal mode switch, they co-operate, and it functions as a dual-socket NUMA system
<clever>
so now you can have twice the cores, and twice the ram (each cpu has its own dram controller)
<moon-child>
interesting
<geist>
yep
<geist>
that's how various models of zen work
<kazinsal>
seems to work pretty well, too
<clever>
geist: now i'm wondering, is there any reason why the 2 cpu's must be on the same motherboard?
<kazinsal>
latency more than anything, I believe
<clever>
if the bios was willing to co-operate, could you cross-link the x16 gpu slot of 2 boards?
<clever>
is that going to be any different from a single mobo, cross-linking 2 sockets with 16 lanes?
<kazinsal>
having it a few centimetres of traces is one thing, 30-50 centimetres is another
<geist>
it speaks a different protocol when linking two cpus together
<geist>
it's reusing the same SERDES lines for different purpose
<clever>
but if you have a gpu based socket, those lanes are likely going directly to the cpu
<kof123>
> having it a few centimetres of traces is one thing, 30-50 centimetres is another you already know which law is still metaphorically at work here lol
<kazinsal>
multiprocessing bus arbitration is super complicated
<clever>
so, cant you just use that non-standard protocol over the gpu pcie socket, into another board?
<clever>
assuming the speed of light issues with the longer cable, dont cause too much problems
<geist>
not if it's not designed to deal with that much clock skew no
<clever>
ah yeah
<clever>
so you would need to keep the skew down, both on the mobo and the extender cable
<geist>
what was the general rule of thumb, something like light travels about 8mm in a nanosecond (ie, 1ghz)
<geist>
or 8cm? 8cm, maybe
<kazinsal>
8cm I think
<kazinsal>
300 billion mm per second
<geist>
i seem to remember something along the lines of a 12 inch sata cable has 2 or 3 bits in flight at any given time
<clever>
so with even pcie gen2 speeds, 5 GT/s, your going to have a dozen bits in the air at any time
<moon-child>
8cm sounds closer to the mark
<moon-child>
I think electricity in copper is like 2/3 speed of light?
<kazinsal>
when I was poking at that multiprocessor 8088 system idea I figured you could probably jam two or three expansion cards with 8088s into the slots closet to the main processor
<kazinsal>
beyond that you've got multiple problems, both distance related and memory/prefetch related
<geist>
protocols like pcie or sata are designed to be point to point transfers, so they can tolerate a fair amount of delay
<geist>
cpu to cpu is similar, but probably needs much less so
<clever>
i think axi is similar?
<kazinsal>
once you get higher and higher clock speeds, you start to get stalls, which get worse if you don't have enough cache
<clever>
the RP1 docs mention that the internal AXI bus can do a max of 16 beat transfers, with a 128bit bus, for a total of 256 bytes
<kazinsal>
for modern systems though there are standards for multiprocessing backplanes with CPUs on cards
<clever>
and if its 256 byte aligned, it can seamlessly translate that to/from a 256 byte pcie packet (the max packet size on the RP1)
<clever>
but, it also mentions the SD controllers have a 64bit bus, so they are moving half the data per clock, and cant keep the pcie interface saturated
<clever>
and will also have worse overheads, due to generating 128 byte pcie packets, since pcie cant stall mid packet and wait for SDIO
<clever>
and i guess its not feasible, to wait for a pair of 16x64bit axi transfers to fill a pcie packet
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<kazinsal>
man I've got some serious cravings for a double shackburger
<kazinsal>
and the nearest shake shack in in lynwood
<kazinsal>
one international border and 50 minutes on the freeway away
<kazinsal>
but god DAMN i feel the need for a double shackburger, bacon cheese fries, and a black and white
<kazinsal>
next time I have a proper amount of time off I am doing a long weekend down to seattle for a proper shake shack visit and a few beers with any osdev locals for sure
<Ermine>
osdev meetup in Seattle?
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<kof123>
i don't know what a black and white is, but yes, this allows for leopard dancing equinox jokes
<kof123>
so yes, seattle seems a good place
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<geist>
dangit did you come down again already?
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<zid>
heat: watched it yesterday
<heat>
did you see the linked video about lost izalith being a swamp?
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<heat>
it makes so much sense
<zid>
I actually fell asleep a couple of minutes before the end and need to watch that still
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<zid>
heat how good is your internet, I wanna play new turf masters
<zid>
neo*
<zid>
same thing
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<zid>
heat_: what's popcorn in lisbon
<heat_>
what
<zid>
WHAT'S THE WORD FOR POPCORN IN LISBONIA
<heat_>
pipocas
<zid>
hah
<zid>
what about cheese
<heat_>
queijo
<zid>
hah
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<Ermine>
pipocas
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<heat_>
linox
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<heat_>
i wonder, are x86 smallers nops more efficient than larger nops?
<heat_>
like will a 1-byte nop have less overhead than a 4-byte nop if you forget icache locality
<mcrod>
hi
<niceperson>
how many 1 byte nops would you plop there mate
<niceperson>
you are fucking with instruction decoders
<mcrod>
how many licks does it take to get to the center of a tootsie pop
<niceperson>
1 gog
<heat_>
niceperson, the question isn't 1 4-byte nop vs 4 1-byte nops, but if there's any actual measurable difference in decoding them
<niceperson>
i don't know, but i don't think that's a real quesiton
<niceperson>
if you can get away with a shorter nop sequence, why would you even try a longer one
<heat_>
bcuz you sometimes can't know
<heat_>
for instance, the jump label stuff i have for riscv needs to account for one instruction in the common case, but maybe two if the jump is super long, so i need 2 nops there
<heat_>
and there's a similar problem where jumps could be relaxed to jmp imm8 so a 5-byte nop is too large
<heat_>
there's probably a similar question there to be had on jmp imm8 vs jmp imm32
<heat_>
is decoding actually measurably slower or is any of the (granted, little) impact just worse instruction locality
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<moon-child>
I think every cycle it takes a fixed number of bytes and tries to decode <=4 instructions from it
<moon-child>
with possible stalls or slowness if you use a 'complicated' encoding
<moon-child>
(though they might be getting up to 6 instructions now? Same principle either way)