09:04 <Shatur> I have a core in Verilog. Are there any examples of integrating it into LiteX? Wiki says that core 1 is a Verilog core, but what is it and where can I find it?

10:04 <zyp> it's a theoretical example

10:05 <zyp> examples on how to integrate it is on the same wiki page you're already looking at

10:06 <zyp> you don't need to do anything special in the verilog, and on the python side you only need the Instance() to invoke it, as well as platform.add_source()

11:07 <Shatur> Oh, got it, thanks. I generated the module using `litex_read_verilog`, will try to add sources.

12:34 <somlo> geertu: for some reason I'm not getting notified of PRs in litex-hub/linux, so I never saw PR #12. This happened before, and I'm sorry :(

12:34 <somlo> but I'll take care of PR #13 today :)

12:35 <somlo> I think the only reason I found out about #13 is because you said `@gsomlo` in one of the comments :)

13:03 <geertu> somlo: Good to know ;-)

13:04 <geertu> Actually you can take both right now, as the pwm .apply() callback has existed for a while.

14:29 <somlo> geertu: ok so #13 isn't just an updated take on #12 -- I'll look at both carefully then, and apply them to the `litex-rebase` branch

14:30 <somlo> also, _florent_ -- do you know what I'd need to do to get pinged automatically on litex-hub/linux PRs ? Is that something I can already do with the privileges I have, or do I need "air support" ? :)

18:40 <mithro> somlo: We can probably give you access

19:31 <_florent_> jevinskie[m]: the antmicro folks probably sleep, but are almost an army :)

19:51 <_florent_> somlo: If you watch the repo you should be pinged on new PRs even if not mentioned.

19:54 <somlo> _florent_: thanks, I switched to "watch all activity" (might need to go "custom" depending on the level of activity :)

19:55 <somlo> I just want to stop missing geertu's PRs against litex-rebase :D