_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<cr1901> _florent_: When you're around, would you be willing to explain the comment on this line here about the PLL phase? https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/trenz_tec0117.py#L100
<pepijndevos[m]> What options are there on an ice40 to run litex when the bitstream is loaded in spi slave mode by an esp32? https://www.bodge.team/docs/badges/mch2022/
<tpb> Title: MCH2022 badge | BADGE.TEAM (at www.bodge.team)
<tnt> IMHO is a custom bootloader and wrap the ESP<->iCE40 comm stuff we have made as a wishbone peripheral for your SoC.
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<jevinskie[m]> Ok, I got the pads/signals all hooked up with VPI. Now I need to turn the event loop inside out or…
<jevinskie[m]> something… since verilator’s event loop is driven by the c++ harness and vpi just gives me callbacks