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<Felkin>
_florent_: In regards to the U255C question, you were right, after looking deeper into the entire new vitis flow, it's practically identical to the SDx flow if using XRT. The issue raised by Sebastien https://github.com/enjoy-digital/litex/pull/1255 was actually invaluable, I modified his code to allow 'Vitis compatible IP generation for .xo
<Felkin>
generation" which can then pass to vitis for .xclbin generation.
<Felkin>
Only issue is that Sebastien's test case was just mimicking axi interfaces, rather than actually doing anything with them internally so I didn't get to test the .xo in XRT's environment yet. I assume the best example we have for this sort of kernel in Litex that inputs a few axis and an axi_lite interface would be the DRAM core right? The vitis
<Felkin>
flow example they have for xrt is some adder kernel, I'd try to switch up the DRAM to that, unless we have better examples around
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