_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<xenador77> I think I'm finally close to done with the target/platform files for the upduino_v3 board, but I'm getting an error from yosys that doesn't make sense (to me) https://pastebin.com/Uc0N51Vz
<tpb> Title: Litex/Upduino_v3: ERROR package does not have a pin named '22' (on line 2) - Pastebin.com (at pastebin.com)
<xenador77> Info: constrained 'clk12' to bel 'X12/Y31/io1' \ERROR: Loading PCF failed.
<xenador77> 22 is a number listed under connectors in my platform file
<xenador77> _connectors = [ ("J2", "37 36 39 38 43 46 42 45 44 49 48 51 50 41"),
<xenador77> ("J3", "25 18 22 23 24 29 31 20 16 13 3 8 9 4 5 2 0 6"), ]
<xenador77> Never mind I think I figured it out, 22 is SPI_VCC and can't be used as GPIO
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