_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<Shatur> To include my own cores into litex_sim I need copy `litex_sim.py` and edit it?
<Shatur> Or how can I try to simulate my board on litex_sim?
<_florent_> Shatur: you can copy litex_sim and customize it yes with your cores/peripherals
<Shatur> Thanks for the info!
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<DerekKozel[m]> Has anyone looked at the Linux dma_buf interface and LitePCIe?
<somlo> _florent_: I think the new "generic toolchain" changes are breaking (at least rocket) builds (on ecpix5): https://pastebin.com/0XvvHX6Z
<tpb> Title: $ litex-boards/litex_boards/targets/lambdaconcept_ecpix5.py --build \ - Pastebin.com (at pastebin.com)
<somlo> my other attempt to build on the nexys video works (with vivado) -- but trellis seems to have a regression