_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<_florent_> Hi
<_florent_> thanks mithro, for some of the points listed in the link, I consider some are implicit for LiteX: Code of conduct and being respectful to each other. I found sad having to have a code of conduct in a project or having to say you have to be respectful, and I consider than anyone not doing this naturally probably has nothing to do in the LiteX community, so we'll just politely let them understand (be evasive in answer, let them
<_florent_> wait, etc...) and they'll leave.
<_florent_> jevinskie[m]: we have a vga framebuffer in the simulator in the past, but this hasn't been re-integrated (yet...):
<_florent_> this was a very simple PoC using SDL
<_florent_> imgui could be really interesting to also be able to look at/control/force internal signals during the simulation
<_florent_> ie to create an interactive simulator environment
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<jevinskie[m]> Yeah at least with VPI it’s easy to get access to internal symbols using iterators over the modules. I think verilator would need fishing signals to the top level before compilation