<jevinskie[m]>
Oh my… antmicro added dynamic scheduling to verilator so stuff like #delay works. I wonder if it can run the micron ddr3 model or macronix SPI model (a big part of why I wanted to support iverilog/Questa) :3 let’s see!
<remy_>
Hi, first of all I would like tot thank you about all the work putted into this wonderful project. But I'm somehow stuck for a month now with a problem of code execution. I built my own riscv toolchain with the Linux-with-Litex with the VexRiscV as a target of my C++ code. As I need to use libraries/peripherals from Linux, I built the linux version of the Toolchain and tried a simple "Hello World" using iostream library. But I get a weird
<remy_>
output error saying that it has an "unhandled signal 7 code 0x1 at 0x95bca894 in ld-linux-riscv32-ilp32.so.1". Did you ever had this error ? Do you konw if there is any way to solve it ? Thank you
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<somlo>
trabucayre: thanks, PR 1352 did indeed fix the issue