07:28 <geertu> somlo_: Similar to the other changes in Commit 4ba0b2c294fe6919 ("fpga: mgr: Use standard dev_release for class driver")

07:28 <geertu> I can make it a patch, but it'll be compile-tested only, too

07:28 <geertu> make a patch

08:17 <geertu> somlo_: Peanut: https://github.com/litex-hub/linux/pull/11

12:38 <likewise> I am having difficulty getting the Alveo U50 OpenOCD ->  BSCANE2 to work for RISC-V  (both with VexRiscv debug, and RISC-V DM compliant debug). Does anyone know the JTAG IR codes for the U50? They are 12-bit but the Ultrascale documentation only documents the 6-bit codes for non-SSI devices.

12:41 <somlo_> geertu: thanks, applied!

12:42 <somlo_> _florent_: "ERROR:SoC:rocket CPU not supported, supporteds: None, picorv32, ..." :)

12:42 <somlo_> _florent_: presumably due to PR 1171 ?

14:41 <Peanut> geertu: I will try your patch in a few hours, I'm currently in the office.

16:03 <_florent_> somlo_: sorry, I'll fix this!

16:48 <_florent_> somlo_: it should be fixed

17:29 <somlo_> _florent_: thanks, it's building now (takes about 70 minutes on the VM I'm using for nexys_video, vs. 25-30 minutes for nexys4ddr :)

17:29 <somlo_> but no reason to expect anything other than "it'll work", now that it's building

17:31 <somlo_> I started using the nexys_video because of sata, but the build time taking twice as long is ever so slightly annoying for my "manual CI" process ;)

17:42 <_florent_> somlo_: For SATA development, you should probably switch back to the 1 core version (if that's not what you are already doing).

18:18 <somlo_> good point, I *am* building the 4-core full (fpu-capable) model, that explains things :)

18:20 <somlo_> _florent_: did you get a chance to try the bitstream I sent on your SATA hardware?

18:21 <somlo_> (because I get nothing with my setup, regardless of vexriscv vs. rocket cpu selection)

19:07 <mithro> somlo_: Any idea why rocket is not listed in https://github.com/enjoy-digital/litex/blob/d1746e1286de909ec679a84712e2eececb08491e/litex/tools/litex_json2dts_linux.py#L34-L44 ?

19:31 <somlo_> mithro: we haven't (yet) taught litex_json2dts_linux.py how to support rocket CPUs

19:33 <somlo_> long answer: part of the chisel-generated files during rocket-chip elaboration consists of a sample .dts file, which should be considered the "authoritative" description of the cpu

19:33 <mithro> I guess json2dts_linux.py could just find and include that dts fragment?

19:34 <somlo_> but it changes from one model to another (standard vs. linux vs. full), and it's noth a 100% straightforward cut'n'paste of a (section of) the chisel-generated .dts into litex_json2dts_linux.py output

19:34 <somlo_> so in other words "it's a bit of a project" :)

19:34 <mithro> We should also add microwatt there too

19:35 <somlo_> not a super difficult project mind you, but still someone (me?) needs to sit down and give it some careful thought :)

21:00 <_florent_> somlo_: Sorry yes I wanted to test it haven't spent the time to setup the hardware, I'll do it tomorrow morning

21:19 <_florent_> mithro: I would first like we finish things we are working on before going in other directions, especially for the thing you said we "should" do and then seem to forget :)

22:37 <Peanut> geertu: I've just built buildroot + kernel with commit hash e32411f3bfe386de58cfa3df2d954c5bdb3040a9 on the litex-rebase branch. This includes your PR from today. This results in a working 5.16.0 kernel on my ButterStick.