_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<jevinskie[m]> I've addresses your comments on the JTAG and ethernet PRs and rebased them standalone against master. Also added one to fix VCD timestamps in litescope by using the samplerate. ;)