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<
MoeIcenowy>
oops GW1NR-9C QN88P PSRAM has two chips
<
MoeIcenowy>
and their port definition just doubles the width of one port
<
MoeIcenowy>
(the PSRAM is in fact HyperRAM too and can be driven with litehyperbus
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MoeIcenowy>
weird, what should I do...
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MoeIcenowy>
well a top design port can only be requested once, but I can then slice it...
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_florent_>
MoeIcenowy: I started the HyperRAM port on the 4K, it was compiling correctly but not working yet, I haven't investigated yet
<
_florent_>
this should be a bit similar on the 9K
<
tpb>
Title: Sipeed Tang 4K ramblings - jaeblog jaeblog (at justanotherelectronicsblog.com)
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