_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<Guest53> @mm001: The output of the streamer is tied to a UDP port, which typically has a width of 8bits. So yes, you can have a streamer that has 32bit width, and you can use a StrideConverter to convert down from 32 to 8bits. As long as you don't produce data too fast, this should work just fine.
<Guest53> So in a way you are right, you can change the stream.py
<Guest53> and potentially make it more generic taking an arbitrary 8*n bitwidth and add a strideconverter in between
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